Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal

High-precision analog-to-digital converter (ADC) testing is a challenging problem because of its stringent requirement on a test signal´s linearity. This paper introduces a method that uses a nonlinear stimulus signal to test the linearity of high-resolution pipelined and cyclic ADCs by exploiting their architecture property. Simulation and experiments show that 16-bit ADCs can be tested to 1-LSB accuracy by using a 7-bit linear signal. This approach provides a solution to both the production and on-chip testing problems of high-resolution ADCs.