Identification of DRAM sense-amplifier imbalance using hot-carrier evaluation

A study of the cause of an inherent imbalance in a DRAM sense amplifier is presented. Refresh time measurements were used to assess this imbalance before and after hot-carrier stress has occurred. The stress effect on the sense amplifier was simulated using a circuit hot-electron effect simulator. This analysis has identified that the latch transistor threshold voltage variation, rather than layout capacitance difference, is the cause of the original imbalance