Designing the MPC105 PCI bridge/memory controller

Author

Wang, Karl ; Bryant, Chris ; Carlson, Mike ; Elmer, Tom ; Harris, Adrian ; Garcia, Michael ; Hui, C.S. ; Leong, C.K. ; Reynolds, Brian ; Tang, Raymond ; Weber, Laura ; Wenzel, Jim ; Wilson, Glen ; Becker, Mike

Author_Institution

Somerset Design Center, Austin, TX, USA

Volume

15

Issue

2

fYear

1995

fDate

4/1/1995 12:00:00 AM

Firstpage

44

Lastpage

49

Abstract

The MPC105 peripheral component interconnection bridge/memory controller provides a platform-specification-compliant bridge between Power PC microprocessors and the PCI bus. With it, designers can create systems using peripherals already designed for a variety of standard PC interfaces. This bridge chip also integrates a secondary cache controller and high-performance memory controller that supports DRAM or synchronous DRAM and ROM or flash ROM

Keywords

DRAM chips; microcontrollers; peripheral interfaces; DRAM; MPC105 PCI bridge/memory controller; PCI bus; Power PC microprocessors; ROM; flash ROM; high-performance memory controller; platform-specification-compliant bridge; secondary cache controller; standard PC interfaces; synchronous DRAM; Bridges; Buffer storage; CMOS technology; Computer buffers; Control systems; Design optimization; Packaging; Random access memory; Read only memory; Read-write memory;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.372351

Filename

372351