• DocumentCode
    752934
  • Title

    Min-cut placement with global objective functions for large scale sea-of-gates arrays

  • Author

    Takahashi, Kazuhiro ; Nakajima, Kazuo ; Terai, Masayuki ; Sato, Koji

  • Author_Institution
    Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
  • Volume
    14
  • Issue
    4
  • fYear
    1995
  • fDate
    4/1/1995 12:00:00 AM
  • Firstpage
    434
  • Lastpage
    446
  • Abstract
    We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms were developed based on a single local optimization function, called the sequential cut line objective function. Our algorithm incorporates global objective functions into this traditional framework of min-cut placement. In particular, we introduce a new global objective function based on the congestions for cut lines and use it for the selection of their sequence. We also use the total cut value objective function in the determination of the sizes and connectivities of clusters that are to be used in the early stages of min-cut partitioning. The incorporation of such global objective functions yields additional reductions of wire congestions in the entire as well as local chip areas. With the automatic selection and use of such clusters and a cut line sequence, our algorithm can produce, in a short time and at a low cost, final placement results that achieve the 100% completion of wiring on chips of fixed sizes. This has led to its successful production use, having generated more than 400 CMOS sea-of-gates array chips of 1.5 K to 150 K raw gates
  • Keywords
    CMOS logic circuits; application specific integrated circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; logic arrays; logic partitioning; CMOS chips; automatic selection; cut line sequence; global objective functions; large scale SOG arrays; min-cut based placement algorithm; min-cut partitioning; sea-of-gates arrays; total cut value objective function; wire congestion reduction; Application specific integrated circuits; Circuit simulation; Clustering algorithms; Costs; Large-scale systems; Partitioning algorithms; Production systems; Simulated annealing; Wire; Wiring;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.372369
  • Filename
    372369