Model for CMOS/SOI single-event vulnerability

A lumped-parameter model derived from transistor characterization data has been used in SPICE analyses to study and predict the single-event-upset thresholds for SIMOX SOI (separation by implantation of oxygen, silicon-on-insulator) SRAMs (static random-access memories) with a variety of cell designs. The modeling of CMOS/SOI transistors with fully bottomed sources and drains includes direct representation of the parasitic lateral bipolar structure. Results indicate that, in the SOI devices investigated, single events simulate a localized bipolar response, even in devices with bodies electrically tied to active nodes. The bipolar response enhances the destabilizing effect of an ion event. The total current impulse contributing to upset can be significantly greater than that produced by direct ionization within the hit transistor, i.e., devices can be upset by ions that deposit less than the total charge required to initiate logic state reversal. In light of this, advanced CMOS/SOI-SOS logic with short channel lengths (and therefore significant parasitic bipolar gain) may exhibit critical LETs (linear energy transfers) lower than expected from simple scaling rules, and thinning of the active regions may not significantly reduce single-event rates in such CMOS/SOI digital circuits