Non-random single event upset trends

Author

McDonald, P.T. ; Stapor, W.J. ; Campbell, A.B. ; Massengill, L.W.

Author_Institution

US Naval Res. Lab., Washington, DC, USA

Volume

36

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

2324

Lastpage

2329

Abstract

A macroscopic investigation of single-even-upset (SEU) trends for a class of CMOS/NMOS static RAMs exposed to heavy ions and protons has been performed. Analysis of the logical and spatial distribution of upsets as well as individual bit-upset polarity shows the need to consider the effects of peripheral circuitry interactions in understanding and modeling SEU phenomena, with important implications for spacecraft systems designs. Experimental studies and analysis of upset distributions along with SPICE modeling of the potential for word line upsets give a clear indication that upsets resulting from particle strikes on peripheral circuitry are occurring, and that the propagation of upsets along peripheral circuitry can have a serious impact on the numbers of logic word multiple upsets observed, depending on the layout of the device

Keywords

CMOS integrated circuits; MOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; radiation hardening (electronics); random-access storage; CMOS; NMOS; SEU; SPICE modeling; SRAM; bit-upset polarity; effects of peripheral circuitry; heavy ions; logic word multiple upsets; macroscopic investigation; modeling SEU phenomena; nonrandom SEU; particle strikes; propagation of upsets; protons; single event upset trends; spacecraft systems designs; spatial distribution of upsets; static RAMs; upset distributions; word line upsets; CMOS logic circuits; Decoding; Laboratories; Logic devices; MOS devices; Protons; Read-write memory; Single event upset; Space vehicles; System testing;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.45443

Filename

45443