Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing

As process geometries shrink, leakage currents and charge sharing are becoming increasingly critical problems, especially in full-custom circuit designs. Excessive leakage or charge sharing may cause functional failure at some or all operating conditions. Traditional circuit-analysis techniques may be used to verify if leakage currents are within allowable limits so as not to cause functional failures; however, unless the analysis takes into account specific input constraints for the circuit, the results may be overly pessimistic. Similar limitations exist for charge sharing. In this paper, we approach this verification problem symbolically using algebraic decision diagrams (ADDs). Using ADDs allows us to efficiently analyze leakage and charge sharing within a channel-connected region (CCR) as a function of its inputs. Exclusivity constraints are easily included in the analysis, thus allowing for more accurate (and less pessimistic) results. Our approach is general and can be applied to any arbitrary circuit structure, including a mesh. The effectiveness of our approach is demonstrated on circuits from industry used in the Alpha 21264 and 21364 instead of the usual international symposium on circuits and systems or Microelectronics Center of North Carolina benchmarks. We show that such an analysis can lead to up to a 90% difference in worst-case voltage drop. This difference can translate into significant savings in manpower by avoiding the need to verify many unrealizable worst-case conditions with other, more costly, simulation techniques.