Title :
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations
Author :
Dechu, Sampath ; Shen, Cien ; Chu, Chris
Author_Institution :
Micron Technol. Inc., Boise, ID, USA
fDate :
4/1/2005 12:00:00 AM
Abstract :
In this paper, we propose a fast algorithm to construct a performance-driven routing tree with simultaneous buffer insertion and wire sizing in the presence of wire and buffer obstacles. Recently, several algorithms have been published addressing the routing tree construction problem. However, all these algorithms are slow and not scalable. In this paper, we propose an algorithm which is fast and scalable with problem size. The main idea of our approach is to specify some important high-level features of the whole routing tree so that it can be broken down into several components. We apply stochastic search to find the best specification. Since we need very few high-level features, the size of stochastic search space is small and can be searched in very little time. The solutions for the components are either pre-generated and stored in lookup tables, or generated by extremely fast algorithms whenever needed. Since it is efficient to obtain solutions for components, it is also efficient to construct and evaluate the whole routing tree for each specification. Experimental results show that, for trees of moderate size, our algorithm out performs the previous algorithms in both quality and runtime.
Keywords :
circuit CAD; circuit layout CAD; network routing; table lookup; trees (electrical); Steiner tree; buffer insertion; interconnect optimization; lookup tables; obstacle considerations; routing tree construction algorithm; stochastic search space; wire sizing; Circuit optimization; Delay; Integrated circuit interconnections; Routing; Runtime; Stochastic processes; Table lookup; Topology; Very large scale integration; Wire; Buffer insertion; Steiner tree; interconnect optimization; wire sizing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.844107