• DocumentCode
    753292
  • Title

    Finite memory test response compactors for embedded test applications

  • Author

    Rajski, Janusz ; Tyszer, Jerzy ; Wang, Chen ; Reddy, Sudhakar M.

  • Author_Institution
    Mentor Graphics Corp., Wilsonville, OR, USA
  • Volume
    24
  • Issue
    4
  • fYear
    2005
  • fDate
    4/1/2005 12:00:00 AM
  • Firstpage
    622
  • Lastpage
    634
  • Abstract
    This paper introduces a new class of finite memory compaction schemes called convolutional compactors (CCs). They provide compaction ratios of test responses in excess of 100×, even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. The CCs can also be used to significantly enhance conventional multiple input signature registers. Experimental results presented in the paper demonstrate the efficiency of convolutional compaction for several industrial circuits.
  • Keywords
    compaction; design for testability; embedded systems; convolutional compactors; design for testability; embedded test; error detection; failing scan cell diagnosis; finite memory compaction schemes; finite memory test; industrial circuits; multiple input signature registers; response compactors; spatial compactors; test response compaction; time compactors; Associate members; Automatic test pattern generation; Built-in self-test; Carbon capture and storage; Circuit testing; Compaction; Design for testability; Registers; Semiconductor device testing; Time factors; Convolutional compactors (CCs); design for testability (DFT); embedded test; spatial compactors; test response compaction; time compactors; unknown states;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2005.844111
  • Filename
    1411939