Hybrid Clock Recovery for a Gigabit POF Transceiver Implemented on FPGA

Author

Ramirez, J. ; Nespola, Antonino ; Straullu, Stefano ; Savio, Paolo ; Abrate, Silivo ; Gaudino, Roberto

Author_Institution

PhotonLab, Ist. Superiore Mario Boella, Turin, Italy

Volume

31

Issue

18

fYear

2013

fDate

Sept.15, 2013

Firstpage

2988

Lastpage

2993

Abstract

In this paper, we present a clock recovery system implemented on field programmable gate array and integrated to the Gigabit Ethernet media converter for PMMA SI-POF developed within the framework of the POF-PLUS EU Project. We demonstrate timing synchronizing using only one sample per symbol from a highly distorted and attenuated 2-PAM signal without requiring any sort of preequalization. This is achieved by means of a hybrid analog-digital PLL with a timing error detector based on a modified version of the Müller and Mueller algorithm, a loop filter, and a VCXO.

Keywords

field programmable gate arrays; local area networks; optical transceivers; phase locked loops; synchronisation; 2-PAM signal; FPGA; Müller algorithm; Mueller algorithm; PMMA SI-POF; POF-PLUS EU Project; VCXO; clock recovery system; field programmable gate array; gigabit Ethernet media converter; gigabit plastic optical fibre transceiver; hybrid analog-digital PLL; hybrid clock recovery; loop filter; phase locked loops; timing error detector; Clocks; Field programmable gate arrays; Media; Optical fibers; Phase locked loops; Synchronization; Clock recovery (CR); DSP; field programmable gate array (FPGA); gigabit ethernet; optical communications; phase-locked loop (PLL); polymer optical fiber; timing error detector (TED);

fLanguage

English

Journal_Title

Lightwave Technology, Journal of

Publisher

ieee

ISSN

0733-8724

Type

jour

DOI

10.1109/JLT.2013.2276767

Filename

6576151