Title :
A capacitorless double-gate DRAM cell
Author :
Hu, Chenming ; King, Tsu-Jae ; Chenming Hu
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
6/1/2002 12:00:00 AM
Abstract :
A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates and thin body reduce off state leakage and. disturb problems. Dopant fluctuations, which can be particularly important in high-density arrays, are avoided by using a thin, lightly doped body. The cell´s large body coefficient ((dV/sub T/)/(dV/sub BD/) transforms small gains of body potential into increased drain current. MEDICI simulations for 85/spl deg/C show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies.
Keywords :
CMOS memory circuits; DRAM chips; MOSFET; leakage currents; 85 degC; MEDICI simulations; capacitorless double-gate DRAM cell; disturb problems reduction; dopant fluctuations; dynamic RAM; high density DRAM technologies; high-density arrays; offstate leakage reduction; scaled CMOS; thin lightly doped body; CMOS technology; Current measurement; Fluctuations; Impact ionization; MOSFETs; Medical simulation; Optical arrays; Random access memory; Silicon on insulator technology; Threshold voltage;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2002.1004230