Leakage power bounds in CMOS digital technologies

The estimation of maximum and minimum leakage consumption for nominal values of the processing parameters is addressed. Tight upper and lower bounds of both extremes are found. In addition, input vectors producing a consumption close to these extremes are obtained. To solve this NP-complete problem, a new hierarchical method based on automatic test pattern generation (ATPG) tools is proposed. The results obtained are compared with Monte Carlo simulations and alternative approaches based. on other heuristics. The results obtained show that the maximum and minimum leakage consumption is estimated with an error lower than 8%. For the largest circuits, c6288 and c7552, the maximum error is lower than 1.3%. The results show that the method compares favorably with alternative approaches