Leakage power bounds in CMOS digital technologies

Author

Ferré, Antoni ; Figueras, Joan

Author_Institution

Departament d´´Enginyeria Electronica, Univ. Politecnica de Catalunya, Barcelona, Spain

Volume

21

Issue

6

fYear

2002

fDate

6/1/2002 12:00:00 AM

Firstpage

731

Lastpage

738

Abstract

The estimation of maximum and minimum leakage consumption for nominal values of the processing parameters is addressed. Tight upper and lower bounds of both extremes are found. In addition, input vectors producing a consumption close to these extremes are obtained. To solve this NP-complete problem, a new hierarchical method based on automatic test pattern generation (ATPG) tools is proposed. The results obtained are compared with Monte Carlo simulations and alternative approaches based. on other heuristics. The results obtained show that the maximum and minimum leakage consumption is estimated with an error lower than 8%. For the largest circuits, c6288 and c7552, the maximum error is lower than 1.3%. The results show that the method compares favorably with alternative approaches

Keywords

CMOS digital integrated circuits; Monte Carlo methods; automatic test pattern generation; circuit simulation; computational complexity; leakage currents; logic simulation; CMOS digital technologies; Monte Carlo simulations; NP-complete problem; automatic test pattern generation; heuristics; hierarchical method; input vectors; leakage power bounds; lower bounds; nominal values; processing parameters; upper bounds; Automatic test pattern generation; CMOS technology; Circuit testing; Energy consumption; Leakage current; NP-complete problem; Power dissipation; State estimation; Subthreshold current; Threshold voltage;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2002.1004317

Filename

1004317