Title :
A 900-Mb/s CMOS data recovery DLL using half-frequency clock
Author :
Maillard, Xavier ; Devisch, Fréedéeric ; Kuijk, Maarten
Author_Institution :
ETRO, Vrije Univ., Brussels, Belgium
fDate :
6/1/2002 12:00:00 AM
Abstract :
A data recovery delay-locked loop (DILL) for nonreturn-to-zero (NRZ) data transmission is described. A reference clock is delayed for triggering a latch that samples the incoming NRZ data stream. The data rate can be twice the reference clock frequency. The circuit has a proportional nondead-zone sampling phase detector that also serves the role of charge pump. A self-correcting function reduces the problem of the finite phase capture range associated with conventional DLLs. The prototype circuit is fabricated in 2.5-V 0.25-μm CMOS and occupies an area of only 270 × 50 μm2. It is demonstrated that at 900-Mb/s NRZ data, jitter is reduced from 118.2- to 31.3-ps rms jitter for a power consumption of only 3 mW
Keywords :
CMOS digital integrated circuits; clocks; data communication equipment; delay lock loops; phase detectors; synchronisation; timing jitter; 3 mW; 900 Mbit/s; NRZ data transmission; charge pump; clock regeneration; coarse tuning; data recovery delay-locked loop; eye diagram; half-frequency clock; high-speed CMOS; jitter removal; latch triggering; output sample-and-hold function; phase detector; plesiochronous timing; proportional nondead-zone sampling detector; repeater circuit; self-correcting function; synchronization; voltage-control delay line; Circuits; Clocks; Data communication; Delay; Frequency; Jitter; Latches; Optical signal processing; Phase detection; Sampling methods;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.1004575
