Performance and optimization of dipole heterostructure field-effect transistor

Dipole heterostructure field effect transistors (dipole HFETs) have been fabricated in AlGaAs/GaAs. Doped p⁺⁺ and n⁺⁺ planes in the charge control AlGaAs layer form a dipole that creates a considerably larger barrier between the channel and the gate than in conventional heterostructure FETs. This leads to a sharp reduction of the forward-biased gate current in enhancement-mode n-channel devices, a much broader transconductance peak, and a higher maximum drain current in enhancement-mode devices. The authors also outline an analytical theory, supported by numerical modeling, for the optimization of device structures for both enhancement- and depletion-mode devices. This is supported by experimental results obtained from enhancement devices