DocumentCode :
755182
Title :
14-bit CMOS pipeline ADC with dual-calibration
Author :
Dumont, S. ; Gandy, P. ; Erdmann, C. ; Gamand, P.
Volume :
43
Issue :
6
fYear :
2007
Firstpage :
33
Lastpage :
34
Abstract :
A new way of designing a 14-bit pipeline analogue-to-digital converter is described. Combined gain calibration and capacitor mismatch correction permit limiting power consumption and achieve a differential nonlinearity of 0.25LSB in a low-cost digital CMOS process (0.18 mum)
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; calibration; pipeline processing; 0.18 micron; 14 bit; CMOS pipeline ADC; capacitor mismatch correction; differential nonlinearity; digital CMOS process; gain calibration; pipeline analogue-to-digital converter; power consumption limiting;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:20070019
Filename :
4138080
Link To Document :
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