Title :
14-bit CMOS pipeline ADC with dual-calibration
Author :
Dumont, S. ; Gandy, P. ; Erdmann, C. ; Gamand, P.
Abstract :
A new way of designing a 14-bit pipeline analogue-to-digital converter is described. Combined gain calibration and capacitor mismatch correction permit limiting power consumption and achieve a differential nonlinearity of 0.25LSB in a low-cost digital CMOS process (0.18 mum)
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; calibration; pipeline processing; 0.18 micron; 14 bit; CMOS pipeline ADC; capacitor mismatch correction; differential nonlinearity; digital CMOS process; gain calibration; pipeline analogue-to-digital converter; power consumption limiting;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20070019
