CMOS squarer and four-quadrant multiplier

Author

Liu, Shen-Iuan ; Hwang, Yuh-Shyan

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

42

Issue

2

fYear

1995

fDate

2/1/1995 12:00:00 AM

Firstpage

119

Lastpage

122

Abstract

A CMOS squarer and a four-quadrant multiplier using the MOS transistors operated in saturation are presented. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over ±2 V input range and a -3 dB bandwidth of 5 MHz. The total harmonic distortion is less than 2.5% with input range up to ±2 V. The squarer has a nonlinearity error less than 1% over ±1.95 V input range. The second-order effect caused by the mobility reduction is discussed. The proposed circuits will be useful in analog signal-processing applications

Keywords

CMOS analogue integrated circuits; analogue multipliers; analogue processing circuits; harmonic distortion; 2 V; 5 MHz; CMOS squarer; THD; analog signal-processing applications; four-quadrant multiplier; mobility reduction; nonlinearity error; saturation operated MOSFETs; second-order effect; total harmonic distortion; Algorithm design and analysis; Analytical models; Circuits; Iterative algorithms; MOSFETs; Neural networks; Signal processing; Signal processing algorithms; Systolic arrays; Threshold voltage;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.372853

Filename

372853