Bottom-oxide scaling for thin nitride/oxide interpoly dielectric in stacked-gate nonvolatile memory cells

Author

Mori, Seiichi ; Sakagami, Eiji ; Kaneko, Yukio ; Ohshima, Yoichi ; Arai, Norihisa ; Yoshikawa, Kuniyoshi

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

39

Issue

2

fYear

1992

fDate

2/1/1992 12:00:00 AM

Firstpage

283

Lastpage

291

Abstract

The authors present results concerning the nitride-oxide (NO) interpoly dielectric in nonvolatile memories. Optimized NO films with a thick top oxide and a thin nitride structure offer sufficient charge retention capability in the 12-nm effective oxide thickness region. However, this structure shows an anomalous threshold voltage increase due to the back tunneling of electrons from the NO film to a floating gate. Such electrons can be injected into the NO film during programming and baking. The magnitude of this voltage depends on the NO film structure and the electric field during the program and bake procedure. Therefore, these phenomena must be taken into consideration in designing the cell structure and its operating conditions. The results obtained are also useful when considering ONO (oxide-nitride-oxide) scaling in the thin bottom-oxide region for nonvolatile memory applications

Keywords

EPROM; MOS integrated circuits; VLSI; dielectric thin films; integrated circuit technology; integrated memory circuits; nitridation; oxidation; 12 nm; EEPROM; EPROM; ONO films; SiO₂-Si₃N₄ dielectric films; back tunneling of electrons; bottom-oxide region; charge retention capability; floating gate; interpoly dielectric; scaling; stacked-gate nonvolatile memory cells; threshold voltage increase; Capacitors; Dielectric devices; Dielectric thin films; Electrons; Helium; Leakage current; Nonvolatile memory; Random access memory; Threshold voltage; Tunneling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.121684

Filename

121684