Baseband Processing in a High-Speed Burst Modem for a Satellite-Switched TDMA System

We present block diagram designs for the baseband processing modules required to implement high-speed (600 Mbit/s) burst modems for use in TDMA satellite systems. Our main concern is to obtain designs which can be implemented with a minimum of high-speed (ECL) devices so as to reduce design and hardware costs. A major consideration in the modem operation is to accurately synchronize it to a reference frame-marker broadcast by a master earth station. Since frame mark recovery must be done at the full serial bit rate, the proposed design relies on the periodic nature of the frame-marker occurrences to enable utilization of short unique words and simple highSpeed electronics to provide extremely reliable marker recovery with virtually no false alarms (or missing markers), even on very noisy channels. Estimates of false alarm rates and the mean time to lock are given. Considerations of clock stability indicate that short-term (150 ms) instabilities must be on the order of a part in 10⁷in order to maintain proper operation of the synchronization circuitry; such stability also minimizes guard time requirements between bursts from the several ground stations sharing a given transponder.