DocumentCode :
75574
Title :
TSV Cu Filling Failure Modes and Mechanisms Causing the Failures
Author :
Jae Woong Choi ; Ong Lee Guan ; Mao Yingjun ; Yusoff, Hilmi B. Mohamad ; Xie Jielin ; Chow Choi Lan ; Woon Lengv Loh ; Boon Long Lau ; Hong, Linda Liew Hwee ; Lau Guan Kian ; Murthy, Ramana ; Kiat, Eugene Tan Swee
Author_Institution :
Inst. of Microelectron., Agency for Sci., Technol. & Res., Singapore, Singapore
Volume :
4
Issue :
4
fYear :
2014
fDate :
Apr-14
Firstpage :
581
Lastpage :
587
Abstract :
In this paper, we report through-silicon via (TSV) Cu filling failure modes and categorize them into three major regions based on their causes. First, Si etch-related region for the TSV defining. Si etch defects, such as bottom corner notch, Si grass at the bottom, surface roughness, and sponge-like defect, cause Cu seed layer loss at the defect areas. It causes electrical disconnection resulting in the TSV Cu filling failure. Second, Cu seed layer-related region. Defects include poor Cu seed layer step coverage and oxidation of the Cu seed layer from the Cu seed layer deposition until the TSV Cu electroplating from the Cu seed layer deposition. They result in aggrandizing terminal effect, which makes Cu ion reduction at the TSV bottom difficult. Third, Cu electroplating-related region. The most important factor in this region is chemical concentration control because the TSV Cu filling by bottom up filling mainly depends on the cooperation of three additives of suppressor, accelerator, and leveler. Another important factor in the region is current density ramp up rate. It is critical to ramp up the current density with an appropriate rate to prevent pinchoff plating causing voids inside the TSVs. These regions are closely connected with each other and the relationship needs to be understood to overcome the TSV Cu filling failure.
Keywords :
copper alloys; current density; electroplating; etching; failure analysis; integrated circuit packaging; integrated circuit reliability; surface roughness; three-dimensional integrated circuits; voids (solid); 3D IC packaging; Cu; TSV copper filling failure modes; accelerator; additives; aggrandizing terminal effect; bottom corner notch; chemical concentration control; current density ramp up rate; electrical disconnection; electroplating-related region; ion reduction; leveler; seed layer deposition; seed layer loss; seed layer-related region; silicon etch-related region; sponge-like defect; suppressor; surface roughness; through-silicon via; voids; Additives; Chemicals; Current density; Oxidation; Silicon; Surface treatment; Through-silicon vias; Cu electroplating; Cu filling defects; Cu seed layer; Si etch; failure modes; through-silicon via (TSV);
fLanguage :
English
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
2156-3950
Type :
jour
DOI :
10.1109/TCPMT.2014.2298031
Filename :
6722913
Link To Document :
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