Design optimization methodology for deep-submicrometer CMOS device at low-temperature operation

Author

Kakumu, Masakazu ; Peters, Dan W. ; Liu, Hua-Yu ; Chiu, Kuang-Yi

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

39

Issue

2

fYear

1992

fDate

2/1/1992 12:00:00 AM

Firstpage

370

Lastpage

378

Abstract

The design optimization for 0.3-μm channel CMOS technology at liquid-nitrogen temperature (77 K) is described. The tradeoff between circuit performance and reliability for deep-submicrometer CMOS devices at low-temperature operation is theoretically and experimentally examined. A simulator, which selects power-supply voltage and process/device parameters for low-temperature operation, has been developed. Based upon the simulated results, design optimization for low-temperature operation has been proposed to determine power-supply voltage and various process and device parameters. The optimized design has been demonstrated on a 0.3-μm CMOS device, by utilizing electron beam (EB) lithography· Excellent device characteristics and a functional ring oscillator circuit have been obtained at 77 K

Keywords

CMOS integrated circuits; electron beam lithography; integrated circuit technology; integrated logic circuits; optimisation; oscillators; 0.3 micron; 77 K; circuit performance; deep-submicrometer CMOS devices; design optimisation methodology; device characteristics; device parameters; electron lithography; logic gates; low-temperature operation; power-supply voltage; process parameters; reliability; ring oscillator circuit; tradeoff; CMOS technology; Circuit optimization; Circuit simulation; Design optimization; Guidelines; Laboratories; Power supplies; Reliability theory; Temperature; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.121696

Filename

121696