DocumentCode :
755816
Title :
Checking the play in plug-and-play
Author :
Goldstein, Harry
Volume :
39
Issue :
6
fYear :
2002
fDate :
6/1/2002 12:00:00 AM
Firstpage :
50
Lastpage :
55
Abstract :
It´s surprising to realize that buyers of intellectual property (IP) blocks used in system-on-chip (SOC) designs may not be entirely aware of what they´re getting and how it works. But that´s one reason why software for IC design verification is gaining attention: to ensure that those blocks will work as intended, both internally and with other components. Another reason is time to market. SOC providers could shorten their time to market considerably if they didn´t have to spend up to 70 percent of it verifying that their designs will plug and play. SOCs are complex designs that fit most or all of the circuitry required for a cellphone, for instance, or a Bluetooth radio on a single IC. As their numbers and complexity increase, the design verification gap is widening. But help is at hand in a new type of design verification called assertions-based verification, although a looming standards battle threatens to slow its widespread adoption.
Keywords :
circuit CAD; industrial property; integrated circuit design; IC design verification; assertions-based verification; design automation; intellectual property; plug-and-play; standards; system-on-chip; Cellular phones; Circuits; Design engineering; Hardware design languages; Intellectual property; Logic design; Plugs; Software design; System-on-a-chip; Time to market;
fLanguage :
English
Journal_Title :
Spectrum, IEEE
Publisher :
ieee
ISSN :
0018-9235
Type :
jour
DOI :
10.1109/MSPEC.2002.1005639
Filename :
1005639
Link To Document :
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