ESD failure modes: characteristics mechanisms, and process influences

Author

Amerasekera, Ajith ; Van den Abeelen, Werner ; Van Roozendaal, Leo ; Hannemann, Marcel ; Schofield, Paul

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

Volume

39

Issue

2

fYear

1992

fDate

2/1/1992 12:00:00 AM

Firstpage

430

Lastpage

436

Abstract

Electrostatic discharge (ESD) failure modes in advanced CMOS processes have been electrically and physically characterized, and an analysis has been made of the mechanisms of each of the main failure modes. The physical failure modes have been related to the electrical degradation and, therefore, the electrical signatures of the damage mechanisms have been obtained. The distribution of the electrical characteristics after ESD stress, for a given process or design variation, can then be used to identify freak failures and process defects. Investigations of the influence of processing steps such as silicides, lightly doped drains (LDDs), thin gate oxides, bird´s-beak suppression, and barrier metallization on the electrical damage characteristics and the failure modes are presented and analyzed

Keywords

CMOS integrated circuits; electrostatic discharge; failure analysis; integrated circuit technology; CMOS processes; ESD; barrier metallization; bird´s-beak suppression; characteristics; damage mechanisms; electrical degradation; electrical signatures; electrostatic discharge; failure mechanisms; failure modes; freak failures; lightly doped drains; process defects; process influences; silicides; thin gate oxides; CMOS process; Degradation; Electric variables; Electrostatic analysis; Electrostatic discharge; Failure analysis; Metallization; Process design; Silicides; Stress;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.121703

Filename

121703