Experimental investigation of an advanced static VAr compensator

Author

Ekanayake, J.B. ; Jenkins, N. ; Cooper, C.B.

Author_Institution

Dept. of Electr. Eng. & Electron., Univ. of Manchester Inst. of Sci. & Technol., UK

Volume

142

Issue

2

fYear

1995

fDate

3/1/1995 12:00:00 AM

Firstpage

202

Lastpage

210

Abstract

An advanced static VAr compensator (ASVC) employing a three-level inverter is presented. The paper describes the operating principles and construction of a hardware model of this ASVC scheme. The performance of the ASVC is obtained from an experimental study carried out on the laboratory model. The use of the selective harmonic elimination modulation technique (SHEM) to minimise harmonics is explored. Experimental studies have been carried out to determine the effect of the DC-side capacitor on the harmonic performance of the scheme and the open-loop response speed is also evaluated. Finally, the economic feasibility of this scheme is briefly assessed by comparing the ASVC with a conventional thyristor-controlled reactor/fixed-capacitor scheme

Keywords

DC-AC power convertors; economics; invertors; modulation; power capacitors; power system harmonics; static VAr compensators; DC-side capacitor; advanced static VAr compensator; economic feasibility; hardware model; harmonic performance; open-loop response speed; operating principles; performance; power systems; selective harmonic elimination modulation technique; three-level inverter;

fLanguage

English

Journal_Title

Generation, Transmission and Distribution, IEE Proceedings-

Publisher

iet

ISSN

1350-2360

Type

jour

DOI

10.1049/ip-gtd:19951710

Filename

373002