Investigation of SOI-like I-V characteristics for a 64-Mb DRAM SCC MOSFET with a buried drain

The MOSFET structure of a surrounding-high-capacitance cell (SCC) trench cell with a buried drain scaled down for 64-Mb DRAM applications has been studied using the device simulator MINIMOS. For this cell design, the depletion zones of the buried drain can pinch off the substrate at a sufficiently high drain bias. The resulting floating substrate causes sharply increased avalanche carrier generation similar to (but more severe than) the kink effects found in SOI structures. These effects limit the utility of this structure for small-geometry DRAM structures. The mechanism for the enhanced avalanche generation and its dependence on bias conditions and geometry have been studied, and pertinent design rules for punchthrough and pinchoff by the buried drain have been established