The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p+-gate p-channel MOSFETs with fluorine incorporation

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V_TP) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V_TP shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO₂/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V_TP shift