A new analytical model for gated turn-off of thyristors

A two-dimensional analytical model is developed to explain the storage phase of the turn-off mechanism in a gate turn-off thyristor. An expression is obtained from first principles for the position of the `on´ region plasma edge as a function of time, assuming a negative ramp for the gate current. The model contains no fitting parameters and addresses realistic issues such as high-injection effects, variation in the base transport factors, and the physical basis for the minimum `on´ region dimension. At the end of the storage time, the active injecting area of the cathode emitter reaches some minimum value which is calculated by imposing the condition that the supply of holes into the plasma region at that point of time is no longer sufficient for sustaining a flow of electrons across the p base. The model is used to investigate analytically the nature of variation of the storage time with anode current, rate of gate current ramp, and cathode island width. Experimental data are in excellent agreement with analytically predicted values