A novel CMOS-compatible top-floating-gate EEPROM cell for embedded applications

A novel nonvolatile memory top-floating-gate (TFG) device is demonstrated in a CMOS technology. This device differs in both structure and operation to typical split-gate or stacked-gate approaches. The TFG device offers low development cost, low power compliance, and high reliability. It can be fabricated using routine CMOS processing making it clearly competitive to options typically used in the industry. The structure and operation of this novel device structure is described. This is followed by a description of the processing steps required and measured electrical results.