The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Author

Noda, Hideyuki ; Tanizaki, Tetsushi ; Gyohten, Takayuki ; Dosaka, Katsumi ; Nakajima, Masami ; Mizumoto, Katsuya ; Yoshida, Kanako ; Iwao, Takenobu ; Nishijima, Tetsu ; Okuno, Yoshihiro ; Arimoto, Kazutami

Author_Institution

Renesas Technol. Corp., Hyogo

Volume

42

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

804

Lastpage

812

Abstract

Novel circuits and design methodology of the massively parallel processor based on the matrix architecture are introduced. A fine-grained processing elements (PE) circuit for high-throughput MAC operations based on the Booth´s algorithm enhances the performance of a 16-bit fixed-point signed MAC, which operates up to 30.0GOPS/W. The dedicated I/O interface circuits are designed for converting the direction of data access and supporting the interleaved memory architecture, and they are implemented for maximizing the processor core efficiency. Power management techniques for suppressing current peaks and reducing average power consumption are proposed to enhance the robustness of the macro. The circuits and the design methodology proposal in this paper are attractive for achieving a high performance and robust massively parallel SIMD processor core employed in multimedia SoCs

Keywords

fixed point arithmetic; memory architecture; microprocessor chips; parallel architectures; system-on-chip; 16 bit; Booth algorithm; data access; dedicated I/O interface circuits; fine-grained processing elements circuit; fixed-point signed MAC; high-throughput MAC operations; interleaved memory architecture; massively parallel SIMD processor; matrix architecture; multimedia SoC; power management; robust design methodology; CMOS technology; Circuit testing; Design methodology; Energy consumption; Energy efficiency; Energy management; Matrix converters; Parallel processing; Registers; Robustness; CMOS; SIMD; integrated circuits; low power; memory; parallel processor;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.891680

Filename

4140595