Title :
An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage
Author :
Pilo, Harold ; Barwin, Charlie ; Braceras, Geordie ; Browning, Chris ; Lamphier, Steve ; Towler, Fred
Author_Institution :
IBM Syst. & Technol. Group, Essex Junction, VT
fDate :
4/1/2007 12:00:00 AM
Abstract :
This paper describes a 32-Mb SRAM that has been designed and fabricated in a 65-nm low-power CMOS Technology. The 62-mm2 die features read-assist and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms. Hardware measurements demonstrate the fail-count improvements achieved by integrating these techniques. The decrease in fail-count provides a 100-mV improvement of VDDMIN during the read operation. Write operations are also improved, especially with weak NFET cell transistors. The circuit techniques have been replicated on a 72-Mb stand-alone standard SRAM product where the area overhead from the additional circuits is approximately 4%. The 32-Mb SRAM has also been successfully migrated to other yield-learning SRAMs in 45-nm bulk and SOI technologies with minimum circuit changes
Keywords :
CMOS memory circuits; SRAM chips; nanotechnology; 32 Mbit; 45 nm; 65 nm; 72 Mbit; SOI technologies; SRAM chips; bulk technologies; expanded operating voltage range; fail-count improvements; improved manufacturability; low-power CMOS technology; read-assist circuits; stand-alone standard SRAM product; weak NFET cell transistors; write-assist circuits; yield-learning SRAM; CMOS technology; Circuit stability; Fluctuations; Hardware; Integrated circuit measurements; Manufacturing; Paper technology; Random access memory; SRAM chips; Voltage; 65 nm; ${hbox{VDD}}_{rm MIN}$; ${hbox{V}}_{rm MIN}$; Low power; SRAM chips; read assist; write assist;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2007.892153
