A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions

Author

Wong, Koon-Lun Jackie ; Rylyakov, Alexander ; Yang, Chih-Kong Ken

Author_Institution

California Univ., Los Angeles, CA

Volume

42

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

881

Lastpage

888

Abstract

A quarter-rate sampling receiver with a 2-tap decision feedback equalizer (DFE) is implemented in 90-nm CMOS technology for low-power I/O links. An analog sampling and soft-decision technique is introduced to relax the timing critical feedback path of the DFE. The shortened critical path enables better power performance. Error rates are below the measurement capability of 10^-12 with 2³¹-1 PRBS at 6 Gb/s, with an 80-mV differential launch amplitude through a channel with 6.2-dB attenuation at 3 GHz. The receiver draws 4.08 mA from a 1.0-V supply

Keywords

CMOS integrated circuits; decision feedback equalisers; low-power electronics; microwave receivers; mixed analogue-digital integrated circuits; signal sampling; 1 V; 2-tap DFE; 4.08 mA; 5 mW; 6 Gbit/s; 90 nm; CMOS technology; analog sampling; low-power I/O links; quarter-rate sampling receiver; shortened critical path; soft decisions; timing critical feedback path; two-tap decision feedback equalizer; Bandwidth; CMOS technology; Decision feedback equalizers; Delay; Interleaved codes; Intersymbol interference; Power dissipation; Sampling methods; Signal to noise ratio; Timing; Decision feedback equalizer (DFE); I/O link; equalizer; low power; receiver;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.892189

Filename

4140601