An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

Author

Wu, Ting ; Mayaram, Kartikeya ; Moon, Un-Ku

Author_Institution

Sch. of Electr. Eng. & Comput. Sci, Oregon State Univ., Corvallis, OR

Volume

42

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

775

Lastpage

783

Abstract

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm²

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF oscillators; calibration; integrated circuit noise; phase locked loops; timing jitter; voltage-controlled oscillators; 0.13 micron; 0.5 to 2 GHz; 1 MHz; 1 V; 10 mV; 3.95 ps; 9.6 mW; CMOS PLL; VCO supply noise; digital calibration; on-chip calibration; phase-locked loop; ring oscillators; rms jitter; supply voltage sensitivity reduction; voltage controlled oscillator; Calibration; Circuit noise; Energy consumption; Frequency measurement; Jitter; Noise measurement; Noise robustness; Phase locked loops; Ring oscillators; Voltage-controlled oscillators; Digital calibration; phase-locked loop; supply voltage sensitivity; voltage controlled oscillator;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2007.892194

Filename

4140603