Title :
Scalable processor instruction set extension
Author :
Becker, Jürgen ; Thomas, Alexander
Author_Institution :
Karlsruhe Univ., Germany
Abstract :
Coarse-grained reconfigurable platforms are good for parallel data-intensive applications but inefficient for sequential control-dominated code. This article explores the integration of the general purpose Sparc-compliant Leon processor with the Extreme Processing Platform reconfigurable data path. The integration´s goal is to optimize the execution of complex multimedia applications such as MPEG-4.
Keywords :
cache storage; instruction sets; microprocessor chips; pipeline processing; reconfigurable architectures; reduced instruction set computing; Extreme Processing Platform; Sparc-compliant Leon processor; coarse-grained reconfigurable platform; multimedia application; parallel data-intensive application; scalable processor instruction set; Adaptive arrays; Computer architecture; Hardware; MPEG 4 Standard; Microprocessors; Pipelines; Programming profession; Protocols; Space missions; Streaming media;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2005.43
