• DocumentCode
    757061
  • Title

    Design-time application mapping and platform exploration for MP-SoC customised run-time management

  • Author

    Ykman-Couvreur, Ch ; Nollet, V. ; Marescaux, Th ; Brockmeyer, E. ; Catthoor, Fr. ; Corporaal, H.

  • Volume
    1
  • Issue
    2
  • fYear
    2007
  • fDate
    3/1/2007 12:00:00 AM
  • Firstpage
    120
  • Lastpage
    128
  • Abstract
    In an Multi-Processor system-on-Chip (MP-SoC) environment, a customized run-time management layer should be incorporated on top of the basic Operating System services to alleviate the run-time decision-making and to globally optimise costs (e.g. energy consumption) across all active applications, according to application constraints (e.g. performance, user requirements) and available platform resources. To that end, to avoid conservative worst-case assumptions, while also eliminating large run-time overheads on the state-of-the-art RTOS kernels, a Pareto-based approach is proposed combining a design-time application and platform exploration with a low-complexity run-time manager. The design-time exploration phase of this approach is the main contribution of this work. It is also substantiated with two real-life applications (image processing and video codec multimedia). These are simulated on MP-SoC platform simulator and used to illustrate the optimal trade-offs offered by the design-time exploration to the run-time manager
  • Keywords
    Pareto optimisation; microprocessor chips; operating system kernels; system-on-chip; Pareto-based approach; cost optimisation; customised run-time management; design-time application mapping; design-time exploration; multiprocessor system-on-chip; operating system service; platform resource exploration; platform simulator; run-time decision making; run-time manager;
  • fLanguage
    English
  • Journal_Title
    Computers & Digital Techniques, IET
  • Publisher
    iet
  • ISSN
    1751-8601
  • Type

    jour

  • DOI
    10.1049/iet-cdt:20060031
  • Filename
    4140666