DocumentCode
757312
Title
Incremental Verification with Error Detection, Diagnosis, and Visualization
Author
Chang, Kai-Hui ; Papa, David A. ; Markov, Igor L. ; Bertacco, Valeria
Author_Institution
Avery Design Syst., Andover, MA
Volume
26
Issue
2
fYear
2009
Firstpage
34
Lastpage
43
Abstract
Invers is a fast incremental-verification system for physical-synthesis optimization that includes capabilities for error detection, diagnosis, and visualization. Using a new metric called the similarity factor, Invers can help engineers identify potential errors earlier in development. Invers employs traditional verification only when necessary to ensure completeness of the verification flow. It also provides an error visualization interface to simplify error isolation and correction.
Keywords
logic design; logic testing; Invers; error detection; error diagnosis; error visualization; incremental-verification system; similarity factor; verification flow completeness; Boolean functions; Circuit synthesis; Computer bugs; Computer errors; Data structures; Design optimization; Digital systems; Error correction; Signal design; Visualization;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2009.38
Filename
4850409
Link To Document