DocumentCode
757328
Title
Computing and Minimizing Cache Vulnerability to Transient Errors
Author
Zhang, Wei
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL
Volume
26
Issue
2
fYear
2009
Firstpage
44
Lastpage
51
Abstract
Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.
Keywords
cache storage; reliability; cache memories; cache vulnerability; reliability trade-offs; transient errors; Cache memory; Computer crashes; Costs; Error correction; Frequency; Microprocessors; Protection; Reliability; Voltage; Working environment noise;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/MDT.2009.29
Filename
4850410
Link To Document