Title :
Computing and Minimizing Cache Vulnerability to Transient Errors
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL
Abstract :
Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance.
Keywords :
cache storage; reliability; cache memories; cache vulnerability; reliability trade-offs; transient errors; Cache memory; Computer crashes; Costs; Error correction; Frequency; Microprocessors; Protection; Reliability; Voltage; Working environment noise;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2009.29