Stability of N-channel polysilicon thin-film transistors with ECR plasma thermal gate oxide

Author

Lee, Jung-Yeal ; Han, Chul-Hi ; Kim, Choong-ki

Author_Institution

Hyundai Electron. Ind. Co., Kyungki, South Korea

Volume

17

Issue

4

fYear

1996

fDate

4/1/1996 12:00:00 AM

Firstpage

169

Lastpage

171

Abstract

The effects of electrical stress on n-channel polysilicon thin-film transistors (poly-Si TFTs) with electron cyclotron resonance (ECR) plasma gate oxide have been investigated. The plasma-hydrogenerated low-temperature (/spl les/600/spl deg/C) TFT\´s exhibited very a small increase of threshold voltage (/spl Delta/V/sub th/<0.3 V) under the stress conditions (V/sub gs/=15 V, V/sub ds/=0 V /spl sim/15 V, and stress time=5/spl times/10/sup 4/ s). The /spl Delta/V/sub t/h was larger for the stress in the linear region than in the saturation region. It was found that the device degradation for the stress in the saturation region was caused by the hot-carriers. Increase of OFF current was maximum for the stress at V/sub gs/=V/sub ds/ while for the stress at V/sub gs/\n\n\t\t

Keywords

elemental semiconductors; hot carriers; plasma deposition; semiconductor device reliability; semiconductor device testing; silicon; thin film transistors; 0 to 15 V; 5E4 s; ECR plasma thermal gate oxide; N-channel polysilicon thin-film transistors; Si; electrical stress; hot-carriers; linear region; saturation region; stress conditions; stress time; threshold voltage; transconductance degradation; Cyclotrons; Degradation; Electrons; Hot carriers; Plasma stability; Resonance; Stress; Thin film transistors; Threshold voltage; Transconductance;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.485163

Filename

485163