Improvement of breakdown voltage in SOI n-MOSFETs using the gate-recessed (GR) structure

Author

Choi, Jin-Hyeok ; Park, Young-June ; Min, Hong-Shick

Author_Institution

Hyundai Electron. Ind. Co., Kyoungki, South Korea

Volume

17

Issue

4

fYear

1996

fDate

4/1/1996 12:00:00 AM

Firstpage

175

Lastpage

177

Abstract

A gate-recessed structure is introduced to SOI MOSFETs in order to increase the source-to-drain breakdown voltage. A significant increase in the breakdown voltage can be seen compared with that of a planar single source/drain SOI MOSFET without inducing the appreciable reduction of the current drivability. We have analyzed the origin of the breakdown voltage improvement by the substrate current measurements and 2-D device simulations, and shown that the breakdown voltage improvement is caused by the reductions in the impact ionization rate and the parasitic bipolar current gain.

Keywords

MOSFET; characteristics measurement; doping profiles; electric breakdown; impact ionisation; semiconductor device models; semiconductor device reliability; semiconductor doping; silicon-on-insulator; 2D device simulations; SOI n-MOSFETs; current drivability; gate-recessed structure; impact ionization rate; parasitic bipolar current gain; source-to-drain breakdown voltage; substrate current measurements; Analytical models; Breakdown voltage; Current measurement; Doping; Fabrication; Impact ionization; MOSFET circuits; Semiconductor films; Silicon; Substrates;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.485165

Filename

485165