• DocumentCode
    758035
  • Title

    Low-power MIMO signal processing

  • Author

    Wang, Lei ; Shanbhag, Naresh R.

  • Author_Institution
    Microprocessor Technol. Labs., Hewlett Packard Co., Fort Collins, CO, USA
  • Volume
    11
  • Issue
    3
  • fYear
    2003
  • fDate
    6/1/2003 12:00:00 AM
  • Firstpage
    434
  • Lastpage
    445
  • Abstract
    In this paper, we present a new adaptive error-cancellation (AEC) technique, denoted as multi-input-multi-output (MIMO)-AEC, for the design of low-power MIMO signal processing systems. The MIMO-AEC technique builds on the previously proposed AEC technique by employing an algorithm transformation denoted as MIMO decorrelating (MIMO-DECOR) transform. MIMO-DECOR reduces complexity by exploiting correlations inherent in MIMO systems, thereby improving the energy efficiency of AEC. The proposed MIMO-AEC enables energy minimization of MIMO systems by correcting transient/soft errors that arise in very large scale integration signal processing implementations due to inherent process nonidealities and/or aggressive low-power design styles, such as voltage overscaling. We employ the MIMO-AEC in the design of a low-power Gigabit Ethernet 1000Base-T device. Simulation results indicate 69.1%-64.2% energy savings over optimally voltage-scaled present-day systems with no loss in algorithmic performance.
  • Keywords
    MIMO systems; decorrelation; error compensation; signal processing; Gigabit Ethernet 1000Base-T device; MIMO decorrelating transform; MIMO signal processing; MIMO-DECOR; adaptive error-cancellation technique; algorithm transformation; energy efficiency; low-power design styles; multi-input-multi-output-AEC; very large scale integration; voltage overscaling; voltage-scaled present-day systems; Adaptive signal processing; Decorrelation; Energy efficiency; Error correction; MIMO; Signal design; Signal processing; Signal processing algorithms; Very large scale integration; Voltage;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2003.812367
  • Filename
    1218216