DocumentCode :
758116
Title :
Gbit/s lossless data compression hardware
Author :
Núñez, José Luis ; Jones, Simon
Author_Institution :
Dept. of Eng. & Design, Univ. of Bath, UK
Volume :
11
Issue :
3
fYear :
2003
fDate :
6/1/2003 12:00:00 AM
Firstpage :
499
Lastpage :
510
Abstract :
This paper presents the X-MatchPRO high-speed lossless data compression algorithm and its hardware implementation, which enables data independent throughputs of 1.6 Gbit/s compression and decompression using contemporary low-cost reprogrammable field-programmable gate array technology. A full-duplex implementation is presented that allows a combined compression and decompression performance of 3.2 Gbit/s. The features of the compression algorithm and architecture that have enabled the high throughputs are described in detail. A comparison between this device and other commercially available data compressors is made in terms of technology, compression ratio, and throughput. X-MatchPRO is a fully synchronous design proven in silicon specially targeted to improve the performance of Gbit/s storage and communication applications.
Keywords :
data compression; field programmable gate arrays; 1.6 Gbit/s; 3.2 Gbit/s; X-MatchPRO algorithm; full-duplex operation; hardware architecture; high-speed lossless data compression; reprogrammable field programmable gate array technology; synchronous design; throughput; Bandwidth; Compressors; Data compression; Dictionaries; Field programmable gate arrays; Hardware; Paper technology; Probability; Statistical analysis; Throughput;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2003.812288
Filename :
1218222
Link To Document :
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