DocumentCode
758363
Title
Design and Implementation of a High-Speed Descrambling Engine for Multi-stream CableCARD
Author
Jung, Joon-Young ; Kwon, O-Hyung ; Lee, Soo In ; Ahn, Jae-Min
Author_Institution
Div. of Radio & Broadcasting Res., Electron. & Telecommun. Res. Inst., Daejeon
Volume
53
Issue
1
fYear
2007
fDate
2/1/2007 12:00:00 AM
Firstpage
166
Lastpage
171
Abstract
In this paper, we present the hardware design of a high-speed descrambling engine for the multi-stream CableCARD device. The designed descrambling engine has been implemented based on a FPGA. The presented design´s scrambling engine has a parallel processing structure that is extendable according to required input bandwidth. Especially we have verified that the designed descrambling engine supported up to 200 Mbps input bandwidth
Keywords
digital television; field programmable gate arrays; parallel processing; television receivers; FPGA; high-speed descrambling engine; multi-stream CableCARD device; parallel processing structure; Bandwidth; Cable TV; Communication cables; Decoding; Engines; Field programmable gate arrays; Hardware; Multiplexing; Standards organizations; Tuners;
fLanguage
English
Journal_Title
Consumer Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0098-3063
Type
jour
DOI
10.1109/TCE.2007.339520
Filename
4140917
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