• DocumentCode
    759090
  • Title

    VLSI implementation of a selective median filter

  • Author

    Chen, Chun-Te ; Chen, Liang-Gee ; Hsiao, Jue-Hsuan

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    42
  • Issue
    1
  • fYear
    1996
  • fDate
    2/1/1996 12:00:00 AM
  • Firstpage
    33
  • Lastpage
    42
  • Abstract
    The VLSI implementation of a selective median filter for real-time applications is presented. The proposed design is based on a novel bit-level running algorithm with a modular and parallel structure. A chip designed by the cell-based style is demonstrated to show the hardware realization. The performance of the proposed design is also presented
  • Keywords
    CMOS digital integrated circuits; VLSI; digital signal processing chips; image processing; median filters; parallel architectures; pipeline processing; VLSI implementation; bit-level running algorithm; cell-based style; design; hardware realization; modular structure; parallel structure; performance; real-time applications; selective median filter; Algorithm design and analysis; Delay; Filtering; Filters; Hardware; Pipelines; Sorting; Statistics; Throughput; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Consumer Electronics, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0098-3063
  • Type

    jour

  • DOI
    10.1109/30.485459
  • Filename
    485459
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=759090