IC design of an adaptive Viterbi decoder

Author

Chan, Ming-Hwa ; Lee, Wen-Ta ; Lin, Mao-Chao ; Chen, Liang-Gee

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

42

Issue

1

fYear

1996

fDate

2/1/1996 12:00:00 AM

Firstpage

52

Lastpage

62

Abstract

We implement an integrated circuit (IC) design for a decoder of a 64-state binary convolutional code. The decoder is based on a reduced-state adaptive Viterbi algorithm (VA) for which the decoding speed is faster than the standard VA while the error performance remains almost the same. With the adaptive VA, less bits are needed to store and to calculate the metrics of the decoding trellis and less power dissipation is needed, as compared to the standard VA. The IC design is based on a 0.8 μm CMOS technology. The number of quantization levels in the decoding is Q=8

Keywords

CMOS digital integrated circuits; Viterbi decoding; adaptive decoding; convolutional codes; integrated circuit design; 0.8 micron; 64-state binary convolutional code; CMOS technology; IC design; adaptive Viterbi decoder; decoding speed; decoding trellis; error performance; integrated circuit design; power dissipation; quantization levels; reduced-state adaptive Viterbi algorithm; Additive white noise; CMOS integrated circuits; CMOS technology; Convolutional codes; Decoding; Hardware; Power dissipation; Quantization; Sorting; Viterbi algorithm;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.485461

Filename

485461