Title :
Complimentary Polarizers STT-MRAM (CPSTT) for On-Chip Caches
Author :
Xuanyao Fong ; Roy, Kaushik
Author_Institution :
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Spin-transfer torque magnetic random access memory devices (STT-MRAMs) show great promise as a candidate technology for on-chip caches. In this letter, we propose a new STT-MRAM bit-cell structure that is suitable for on-chip caches compared with the standard STT-MRAM bit-cell (SSC). Scalability of our proposed structure is studied with the aid of micromagnetic and circuit simulators. Results show that our proposed bit-cell is more scalable than the SSC, achieving>; 4× better write margin, >; 65% better sensing margin, lower read disturb failures, and subnanosecond sensing delays.
Keywords :
MRAM devices; cache storage; CPSTT; circuit simulators; complimentary polarizer STT-MRAM bit-cell structure; micromagnetic simulators; on-chip caches; sensing margin; spin-transfer torque magnetic random access memory devices; subnanosecond sensing delays; Delay; Magnetic tunneling; Sensors; System-on-a-chip; Torque; Transistors; Writing; Improved dual pillar STT-MRAM; spin-transfer torque MRAM (STT-MRAM); symmetric STT-MRAM write current; true self-reference differential STT-MRAM;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2012.2234079
