Low-resistance ultrashallow extension formed by optimized flash lamp annealing

Author

Ito, Takayuki ; Suguro, Kyoichi ; Tamura, Mizuki ; Taniguchi, Toshiyuki ; Ushiku, Yukihiro ; Iinuma, Toshihiko ; Itani, Takaharu ; Yoshioka, Masaki ; Owada, Tatsushu ; Imaoka, Yasuhiro ; Murayama, Hiromi ; Kusuda, Tatasufumi

Author_Institution

Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan

Volume

16

Issue

3

fYear

2003

Firstpage

417

Lastpage

422

Abstract

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 × 10¹⁸ cm^-3 and the sheet resistance of 13 nm and 700 Ω/sq for As and 14 nm and 770 Ω/sq for BF₂ with junction leakage lower than 1 × 10^-16 A/μm² at 1.5 V were successfully obtained without wafer slip and warpage problems.

Keywords

CMOS integrated circuits; MOSFET; impurities; incoherent light annealing; integrated circuit manufacture; temperature distribution; 1.5 V; 13 nm; 14 nm; Si:BF₂; implantation conditions; implanted impurities activation; junction depth; junction leakage; low-resistance ultrashallow extension; optimized flash lamp annealing; preamorphization; ultrashallow junction; Heating; Impurities; Indium tin oxide; Lamps; MOSFETs; Optimization methods; Rapid thermal annealing; Stress; Temperature; Thermal resistance;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2003.815621

Filename

1219488