Title :
A radiation-hardened 10 K-gate CMOS gate array
Author :
Hatano, Hiroshi ; Yoshii, Ichiro ; Shibuya, Mikio ; Takatuka, Satoru ; Shinohara, Takashi ; Noguchi, Teruyuki ; Yamamoto, Kazuhiko ; Fuji, Hiromichi ; Abe, Ryo
Author_Institution :
Toshiba Res. & Dev. Centre, Kawasaki, Japan
fDate :
12/1/1989 12:00:00 AM
Abstract :
A radiation-hardened 10013-gate complementary metal-oxide-semiconductor (CMOS) gate array with a 5-V supply voltage has been designed and fabricated utilizing Si-gate epi-CMOS technology with two-level metallization. The n-channel (NMOS) and p-channel (PMOS) gate lengths in basic cells are 2 μm. A 100-krad(Si) total-dose radiation hardness has been realized by introducing a thin field oxide between the source and drain diffusion layers and a thick field oxide in NMOS transistors in both the basic cells and the I/O cells, as well as a buried p+ diffusion layer under a poly-Si layer at the p-well edge in the basic cells, without sacrificing speed and performance. The gate array can be used to realize various kinds of radiation-tolerant logic LSIs for space and nuclear plant applications
Keywords :
CMOS integrated circuits; integrated logic circuits; logic arrays; radiation hardening (electronics); 2 micron; 5 V; I/O cells; NMOS gate lengths; NMOS transistors; PMOS gate lengths; Si-gate epi-CMOS technology; basic cells; buried p+ diffusion layer; complementary metal-oxide-semiconductor; drain diffusion layers; p-well edge; performance; poly-Si layer; radiation-hardened 10 K-gate CMOS gate array; radiation-tolerant logic LSIs; speed; supply voltage; thick field oxide; thin field oxide; total-dose radiation hardness; two-level metallization; CMOS technology; Circuits; Degradation; Large scale integration; MOS devices; MOSFETs; Metallization; Radiation effects; Temperature dependence; Threshold voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
