• DocumentCode
    759746
  • Title

    An analytical dishing and step height reduction model for chemical mechanical planarization (CMP)

  • Author

    Fu, Guanghui ; Chandra, Abhijit

  • Author_Institution
    Dept. of Mech. Eng., Iowa State Univ., Ames, IA, USA
  • Volume
    16
  • Issue
    3
  • fYear
    2003
  • Firstpage
    477
  • Lastpage
    485
  • Abstract
    An analytical model for dishing and step height reduction in chemical mechanical planarization (CMP) is presented. The model is based on the assumption that at the feature scale, high areas on the wafer experience higher pressure than low areas. A Prestonian material removal model is assumed. The model delineates how dishing and step height reduction depend on slurry properties (selectivity and Preston´s constants), pad characteristics (stiffness and bending ability), polishing conditions (pressure, relative velocity and overpolishing) and wafer surface geometry (linewidth, pitch and pattern density). Model predictions are in good agreement with existing experimental observations. The present model facilitates understanding of the CMP process at the feature scale. Based on the proposed model, design avenues for decreasing dishing and increasing the speed of step height reduction may be explored through modification of appropriate parameters for slurry, pad and polishing conditions. The proposed model may also be used as a design tool for pattern layout to optimize the performance of the CMP process.
  • Keywords
    chemical mechanical polishing; deformation; planarisation; semiconductor process modelling; surface topography; CMP process; Prestonian material removal model; analytical model; bending ability; chemical mechanical planarization; design tool; dishing; linewidth; overpolishing; pad characteristics; pattern density; pattern layout; pitch; polishing conditions; slurry properties; step height reduction; stiffness; wafer surface geometry; Chemical analysis; Copper; Dielectric substrates; Planarization; Plasma temperature; Predictive models; Semiconductor device modeling; Slurries; Surface resistance; Surface topography;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2003.815202
  • Filename
    1219496