Title :
Partners in platform design
Author :
Tremblay, Marc ; Tirumalai, Partha
Author_Institution :
Sun Microsystems Inc., Mountain View, CA, USA
fDate :
4/1/1995 12:00:00 AM
Abstract :
Modern reduced-instruction-set computer chips have features that lay the groundwork for great performance. They boast circuits that can work at clock frequencies ranging to 300 MHz, pipelines built to continually execute independent operations, and the ability to execute multiple instructions in a single clock cycle. The potential of this hardware can only be realized by sophisticated compiler technology. The best approach to optimal computing performance is to design a processor architecture and a compiler concurrently
Keywords :
instruction sets; microprocessor chips; parallel architectures; pipeline processing; program compilers; reduced instruction set computing; clock frequencies; compiler technology; multiple instructions; pipelines; platform design; processor architecture; reduced-instruction-set computer chips; Circuits; Clocks; Computer aided instruction; Computer architecture; Decoding; Frequency; Pipelines; Registers; Sun; Throughput;
Journal_Title :
Spectrum, IEEE
