Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique

Embedded SRAM bit count is constantly growing limiting yield in systems-on-chip (SoCs). As technology scales into deep sub-100-nm feature sizes, the increased defect density and process spreads make stability of embedded SRAMs a major concern. This paper introduces a digitally programmable detection technique, which enables detection of SRAM cells with compromised stability [with data retention faults (DRFs) being a subset]. The technique utilizes a set of cells to modify the bitline voltage, which is applied to a cell under test (CUT). The bitline voltage is digitally programmable and can be varied in wide range, modifying the pass/fail threshold of the technique. Programmability of the detection threshold allows tracking process variations and maintaining the optimal tradeoff between test quality and test yield. The measurement results of a test chip presented in the paper demonstrate the effectiveness of the proposed technique