Data Traffic Performance of Integrated Circuit- and Packet-Switched Multiplex Structure

Results are developed for data traffic performance in an integrated multiplex structure which includes circuit-switching for voice and packet-switching for data. The results are obtained both through simulation and analysis, and show that excessive data queues and delays will build up under heavy loading conditions. These large data delays occur during periods of time when the voice traffic load through the multiplexer exceeds its statistical average. A variety of flow control mechanisms to reduce data packet delays are investigated. These mechanisms include control of voice bit rate, limitation of the data buffer, and combinations of voice rate and data buffer control. Simulations indicate that these flow control mechanisms provide substantial improvements in system performance.