Statistical carry lookahead adders

Author

De Gloria, Alessandro ; Olivieri, Mauro

Author_Institution

Dept. of Biophys. & Electr. Eng., Genoa Univ., Italy

Volume

45

Issue

3

fYear

1996

fDate

3/1/1996 12:00:00 AM

Firstpage

340

Lastpage

347

Abstract

Addition techniques are divided into fixed-time and variable-time ones. While variable time techniques can achieve log₂(N) average addition time for N-bit operands, the hardware overhead have always made fixed-time adders preferable, such as Carry Lookahead and Carry Select. We present a new variable-time addition technique whose average delay is much lower than log₂(N) and whose overhead is lower than the one of a CLA adder. The new approach is made feasible by a proper application of VLSI dynamic logic design. We show the mathematical proof, the logic implementation, and the VLSI realization of the new adder. We report circuit simulation results and their comparison with the analytical model

Keywords

adders; digital arithmetic; logic design; Carry Lookahead; VLSI design; VLSI dynamic logic design; asynchronous circuits; average delay; carry lookahead adders; completion detecting units; computer arithmetic; logic implementation; mathematical proof; self-timed systems; variable-time addition; Adders; Analytical models; Application software; Circuit simulation; Costs; Delay effects; Digital arithmetic; Hardware; Logic design; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.485572

Filename

485572